1. Field of the Invention
This invention relates to a chip package structure and a process of fabricating the same. More particularly, this invention relates to a chip package structure formed by flip chip bonding and a process of fabricating the same.
2. Brief Description of Related Art
Electronic devices have been increasingly developed to meet demands of digitalization, network, LAN connection and humanization in use. Therefore, high operation speed, multifunctions, integration, compactness and competitive prices are the key features for commercial success. The Chip package technology must catch up the development trend of the electronic devices with high density and compactness. A flip chip technology uses bumps as the connection intermedium to a carrier, which shortens wire length compared to a conventional wire bonding. Short wire length facilitates increase in signal transmission between the chip and the carrier. Therefore, the flip chip technology has become the main stream in the high-pin-count packaging field.
FIG. 1 is a cross-sectional view of a conventional chip package structure formed by a flip chip technology. Referring to FIG. 1, a chip 50 of a chip package structure 40 has an active surface 52 on which a plurality of bumps 60 are respectively mounted. A plurality of bonding pads 54 are formed on the active surface 52. A plurality of contacts 84 are formed on a carrier 80. The chip 50 electrically connects to the carrier 80 via the bonding pads 54, the bumps 60 and the contacts 84.
Furthermore, in order to protect the chip 50 from being damaged due to the moisture and protect the bumps 60 connecting the chip 50 and the carrier 80 from being damaged due to the mechanical stress, an underfill 70 is filled between the chip 50 and the carrier 80. However, since there is a mismatch in coefficient of thermal expansion (CTE) between the chip 50, the bumps 60, the underfill 70 and the carrier 80, the chip package structure 40 tends to fail due to the thermal stress resulting from temperature difference during thermal cycles.
Upper layers of the chip are called as interconnection that consists of a plurality of conductive layers and dielectric layers sandwiched by the conductive layers. When the Young's modulus of the underfill is high, delamination between the conductive layers and the dielectric layers occurs due to the thermal stress, which deteriorates the interconnections and leads to chip failure. Complying with the appearance of the copper process applied in the semiconductor manufacturing technology, the material constituent of the conductive layers and the dielectric layers are from the set of aluminum and silicon dioxide to the set of copper and organic materials. The adhesion between copper and low-k dielectrics is lower than that between aluminum and silicon dioxide. Therefore, delamination between the copper layer and the low-k dielectrics occurs more often.
Furthermore, when the Young's modulus of the underfill is low, the thermal stress tends to cause cracking of bumps near the carrier, and thereby significantly decreasing the reliability of electric connection between the chip and the carrier. Therefore, how to avoid the damage of interconnection of the chip and the bump due to the CTEs mismatch between the chip, the bumps, the underfill and the carrier is an important issue in this field.